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[Model] Support uneven TP3 Qwen3.5/Qwen3Next layouts#47759

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[Model] Support uneven TP3 Qwen3.5/Qwen3Next layouts#47759
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@s0l s0l commented Jul 6, 2026

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Purpose

Enable Qwen3.5/Qwen3Next models whose attention, GDN, and dense-MLP dimensions are not evenly divisible by tensor parallel size. The tested target is dense Qwen3.5 27B NVFP4 with TP=3 and DCP=3 on three PCIe Blackwell GPUs.

This replaces the previous broad experimental branch with a clean rebase onto current main. MTP, DFlash, MoE/EP experiments, low-bit collectives, diagnostics, profiling hooks, and rejected POCs are intentionally excluded.

Approach

  • Add explicit uneven GQA and Gated DeltaNet head partitions with padded local projections and logical checkpoint spans.
  • Add padded merged-column and row-parallel weight loaders, including NVFP4/WNA16 packed dimensions and scalar scales.
  • Pad the dense Qwen MLP intermediate dimension while preserving grouped W4A16 alignment (17408 -> 17472 for TP=3).
  • Size Mamba states and CUDA-graph profiling caches from the actual uneven/DCP geometry.
  • Align Mamba prefill chunks to effective DCP block geometry.
  • Skip construction and loading of the Qwen3.5 visual tower under --language-model-only.
  • Pad and mask the CP LSE correction reduction for non-power-of-two world sizes (N=3, launch width 4).

The generalized DCP validation change is restricted to qwen3_5_text and qwen3_next; other GQA/MQA models retain the previous fail-fast behavior.

Dependencies and duplicate-work check

Searches were run for TP3 Qwen3.5, uneven tensor parallelism, FlashInfer DCP metadata, non-power-of-two DCP, and concurrent partial prefill.

Tests

28 focused pytest tests passed
Ruff passed for every changed Python file
git diff --check passed
direct CUDA DCP3 LSE probe passed for natural-log and base-2 LSE

The focused suite covers uneven attention/GDN partitions, packed NVFP4/WNA16 loaders, padded vocab/MLP shards, Mamba DCP chunk alignment, and CUDA-graph KV sizing.

Model and serving validation

Candidate: nvidia/Qwen3.6-27B-NVFP4, TP=3, DCP=3, FlashInfer 0.6.14, FP8 KV, prefix caching, eager disabled, FULL+PIECEWISE CUDA graphs, no MTP.

  • Server initialized successfully and captured all configured graphs.
  • GPU KV cache: 412,903 logical tokens.
  • Maximum concurrency at 153,600 tokens/request: 2.69x with memory utilization 0.82.
  • Graph memory: approximately 0.51 GiB per GPU.
  • Tool-call sanity returned finish_reason=tool_calls, the requested function, and valid JSON arguments in repeated probes.
  • Partial4 local POC: 4/4 unique long prompts succeeded, 0 errors, 1122.65 prompt tok/s, wall/p50 about 22.7s.
  • Single-stream decode observed on the ABI-overlay candidate: 12.8 tok/s. This is a correctness sanity result, not a final performance claim, because the older binary selected Marlin weight-only FP4.

MTP is excluded because the controlled agent workload regressed from 8/8 in 228.3s without MTP to 7/8 in 294.6s with MTP, despite synthetic decode gains.

AI assistance

AI assistance was used for research, implementation, testing, and preparation of this PR. The submitter reviewed the resulting scope and is responsible for the change end to end.

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github-actions Bot commented Jul 6, 2026

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@mergify

mergify Bot commented Jul 6, 2026

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Documentation preview: https://vllm--47759.org.readthedocs.build/en/47759/

@mergify mergify Bot added documentation Improvements or additions to documentation qwen Related to Qwen models nvidia v1 labels Jul 6, 2026
@s0l s0l force-pushed the exp/tp3-dcp-gdn-128k branch 2 times, most recently from bb7aef3 to a798424 Compare July 6, 2026 16:48

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AI-assisted self-review notes:

  • This is a substantive hardware/topology research PR, not a small cleanup: it targets a real 3 x 16 GiB PCIe/no-NVLink configuration where TP=2 wastes a GPU and default TP=3 is blocked or underutilized by Qwen3.6 non-divisible layouts.
  • The PR is still intentionally Draft/WIP. It should not be treated as merge-ready in its current shape; it likely needs to be split into smaller reviewable PRs if maintainers are interested in the direction.
  • Highest-risk code areas are the non-uniform TP sharding helpers, DCP/KV-cache changes, and experimental DFlash fallback hooks. Any path intended for merge needs focused unit tests plus hardware validation.
  • The DFlash replication hooks are diagnostic only. They are not the recommended production design because DFlash MLP remains incompatible with TP=3 (17408 % 3 != 0) and full replication would likely hurt the memory budget.
  • MTP support on dense 27B TP=3 starts and has healthy short-run acceptance metrics, but performance still needs controlled A/B benchmarking before claiming speedup.
  • DCO is now fixed; duplicate-work checks and AI-assistance disclosure are included in the PR body per AGENTS.md.

@mergify

mergify Bot commented Jul 7, 2026

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This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @s0l.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

@mergify

mergify Bot commented Jul 10, 2026

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This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @s0l.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

@mergify mergify Bot added the needs-rebase label Jul 10, 2026
@s0l s0l force-pushed the exp/tp3-dcp-gdn-128k branch from 0e7cb91 to 657dabc Compare July 10, 2026 11:41
s0l and others added 8 commits July 10, 2026 23:28
Treat the maximum capture size as a token count instead of a block count. Convert attention requirements using the context-parallel effective block size and reserve one state line per request for Mamba caches.

Co-authored-by: Codex <codex@local>
Signed-off-by: s0l <thetrues0l@gmail.com>
Add explicit per-rank mappings for GQA and Gated DeltaNet heads whose layouts are not evenly divisible by tensor parallel size. Pad local projection shards while preserving logical checkpoint spans, and allocate matching Mamba state shapes.

Co-authored-by: Codex <codex@local>
Signed-off-by: s0l <thetrues0l@gmail.com>
Translate logical padded spans through packed parameter indexing for merged column, overlapping GQA, and row-parallel loaders. Preserve scalar scales and fused-checkpoint loading for NVFP4/WNA16 layouts.

Co-authored-by: Codex <codex@local>
Signed-off-by: s0l <thetrues0l@gmail.com>
Use the scheduler's effective block size and the DCP-scaled physical block size when splitting Mamba align-mode prefills. Preserve sub-block chunks that cannot be aligned within the current budget.

Co-authored-by: Codex <codex@local>
Signed-off-by: s0l <thetrues0l@gmail.com>
Skip construction and checkpoint loading of the visual tower when the multimodal configuration requests a language-model-only server.

Co-authored-by: Codex <codex@local>
Signed-off-by: s0l <thetrues0l@gmail.com>
Co-authored-by: Codex <codex>
Signed-off-by: s0l <thetrues0l@gmail.com>
Co-authored-by: Codex <codex>
Signed-off-by: s0l <thetrues0l@gmail.com>
Co-authored-by: Codex <codex>
Signed-off-by: s0l <thetrues0l@gmail.com>
@s0l s0l force-pushed the exp/tp3-dcp-gdn-128k branch from 657dabc to 4e8959a Compare July 10, 2026 20:31
@s0l s0l changed the title [WIP] Experimental Qwen3.6 TP3/DCP3 research and DFlash hooks [Model] Support uneven TP3 Qwen3.5/Qwen3Next layouts Jul 10, 2026
@mergify mergify Bot removed the needs-rebase label Jul 10, 2026
@mergify

mergify Bot commented Jul 12, 2026

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This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @s0l.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

@mergify mergify Bot added the needs-rebase label Jul 12, 2026
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